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Analysis and hardware testing of cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters.

Aboushady, A.A.; Ahmed, K.H.; Jovcic, D.

Authors

A.A. Aboushady

K.H. Ahmed

D. Jovcic

Abstract

This paper focuses on the behaviour of the cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters. Active switches, not designed for fault conditions, are tripped to minimize discharge currents effect on the semiconductor switches. Two levels of device protection are commonly in place; driver level protection monitoring collector-emitter voltage and overcurrent protection with feedback measurement and control. However, unavoidable tripping delay times, arising from factors such as sensor lags, controller sampling delays and hardware propagation delays, impact transient current shape and hence affect the selection of semiconductor device ratings as well as arm inductance. Analytical expressions are obtained for current slew rate, peak transient current and resultant I2t for the cell capacitor discharge current taking into account such delays. The study is backed by experimental testing on discharge of a 900V MMC capacitor.

Start Date Feb 10, 2015
Publication Date Feb 10, 2015
Publisher Institution of Engineering and Technology
Pages 1-7
Institution Citation ABOUSHADY, A.A., AHMED, K.H. and JOVCIC, D. 2015. Analysis and hardware testing of cell capacitor discharge currents during DC faults in half-bridge modular multilevel converters. In Proceedings of the 11th Institution of Engineering and Technology (IET) International conference on AC and DC power transmission, 10-12 February 2015, Birmingham, UK. New York: IET [online], pages 1-7. Available from: https://doi.org/10.1049/cp.2015.0010
DOI https://doi.org/10.1049/cp.2015.0010
Keywords Cell capacitor discharge; DC faults; Driver level protection; Overcurrent protection

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